\doxysection{RTC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_r_t_c___type_def}{}\label{struct_r_t_c___type_def}\index{RTC\_TypeDef@{RTC\_TypeDef}}


Real-\/\+Time Clock.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a2e8783857f8644a4eb80ebc51e1cba42}{TR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a8750eae683cb3d382476dc7cdcd92b96}{DR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a731d9209ce40dce6ea61fcc6f818c892}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a5a7b104d80b48b5708b50cdc487d6a78}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a5f43a11e0873212f598e41db5f2dcf6a}{PRER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ad93017bb0a778a2aad9cd71211fc770a}{WUTR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a37afe665222962031d111527b7fd406b}{RESERVED}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ad7e54d5c5a4b9fd1e26aca85b1e36c7f}{ALRMAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a9816616e1f00955c8982469d0dd9c953}{ALRMBR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ad54765af56784498a3ae08686b79a1ff}{WPR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_aefbd38be87117d1fced289bf9c534414}{SSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a6082856c9191f5003b6163c0d3afcaff}{SHIFTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a1ddbb2a5eaa54ff43835026dec99ae1c}{TSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_aa4633dbcdb5dd41a714020903fd67c82}{TSDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a1e8b4b987496ee1c0c6f16b0a94ea1a1}{TSSSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_aea66ea813830c2f3ff207464794397a4}{CALR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a498ecce9715c916dd09134fddd0072c0}{TAFCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ac5b2e3c0dcdcb569f3fe15dfe3794bc1}{ALRMASSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a249009cd672e7bcd52df1a41de4619e1}{ALRMBSSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ac4ec213226146fa48aa9b29e0e80b3ad}{OR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ab32c76ca1f3bd0f0f46d42c2dfa74524}{BKP0R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a5439bfca3708c6b8be6a74626f06111f}{BKP1R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_aa845c401b24d2ef1049f489f26d35626}{BKP2R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_ac3802c3b17482a0667fb34ddd1863434}{BKP3R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a6131b2f2896c122cf223206e4cfd2bd0}{BKP4R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a0f3a33de81247ec5729e400a1261f917}{BKP5R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a766e2071c5826e3a299ae1cd5bbf06f7}{BKP6R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a9934af6ae6b3f5660204d48ceb2f3192}{BKP7R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a0e7fca11f1c953270ee0ee6028860add}{BKP8R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_abadf1ac26350bf00575428be6a05708b}{BKP9R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a5feba3d5adae3f234b3d172459163c5a}{BKP10R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a8fef38e1e122778601e18f5b757c037a}{BKP11R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a6606b5d249f923aa15ab74b382cbaf7e}{BKP12R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a138903d4681455a660dccbaf3409263d}{BKP13R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_adaae50f5c3213014fb9818eaee389676}{BKP14R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a797f43f9cc1858baebd1799be288dff6}{BKP15R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a181ad73082bde7d74010aac16bd373fc}{BKP16R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a90a305a8e00b357f28daef5041e5a8b1}{BKP17R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a171288f82cab2623832de779fb435d74}{BKP18R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a993f54e8feff9254f795dfd3e000fc55}{BKP19R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a3e391ffa70a17dc5f95a841b5ec7554c}{BKP20R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a170847c24f166be0939a6eaeed7eeeee}{BKP21R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a679ec46535cae5149dc4d84e7c5d985c}{BKP22R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a7836b793c4ecc58a27733329f26550a7}{BKP23R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_abfe68a89c3a7c2620bb0f286d3f58eea}{BKP24R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a052e275100e4b202808fa4bbe9d5515d}{BKP25R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_aaa12210df2df47a6276270a2b7b2d038}{BKP26R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a5879b0d3796b1c291f64dbaa57653624}{BKP27R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_abd26829bfe028b5882d523e7035eb497}{BKP28R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_aa240211cf23c5822f4ac9c690a7a248c}{BKP29R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a32b51e2f18c68ea5af816d1f231b7ec6}{BKP30R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_t_c___type_def_a4bccd0b2feecc2e2159898857bab6d89}{BKP31R}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Real-\/\+Time Clock. 

\label{doc-variable-members}
\Hypertarget{struct_r_t_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_t_c___type_def_ad7e54d5c5a4b9fd1e26aca85b1e36c7f}\index{RTC\_TypeDef@{RTC\_TypeDef}!ALRMAR@{ALRMAR}}
\index{ALRMAR@{ALRMAR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ALRMAR}{ALRMAR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ad7e54d5c5a4b9fd1e26aca85b1e36c7f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+ALRMAR}

RTC alarm A register, Address offset\+: 0x1C \Hypertarget{struct_r_t_c___type_def_ac5b2e3c0dcdcb569f3fe15dfe3794bc1}\index{RTC\_TypeDef@{RTC\_TypeDef}!ALRMASSR@{ALRMASSR}}
\index{ALRMASSR@{ALRMASSR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ALRMASSR}{ALRMASSR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ac5b2e3c0dcdcb569f3fe15dfe3794bc1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+ALRMASSR}

RTC alarm A sub second register, Address offset\+: 0x44 \Hypertarget{struct_r_t_c___type_def_a9816616e1f00955c8982469d0dd9c953}\index{RTC\_TypeDef@{RTC\_TypeDef}!ALRMBR@{ALRMBR}}
\index{ALRMBR@{ALRMBR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ALRMBR}{ALRMBR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a9816616e1f00955c8982469d0dd9c953} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+ALRMBR}

RTC alarm B register, Address offset\+: 0x20 \Hypertarget{struct_r_t_c___type_def_a249009cd672e7bcd52df1a41de4619e1}\index{RTC\_TypeDef@{RTC\_TypeDef}!ALRMBSSR@{ALRMBSSR}}
\index{ALRMBSSR@{ALRMBSSR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ALRMBSSR}{ALRMBSSR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a249009cd672e7bcd52df1a41de4619e1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+ALRMBSSR}

RTC alarm B sub second register, Address offset\+: 0x48 \Hypertarget{struct_r_t_c___type_def_ab32c76ca1f3bd0f0f46d42c2dfa74524}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP0R@{BKP0R}}
\index{BKP0R@{BKP0R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP0R}{BKP0R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ab32c76ca1f3bd0f0f46d42c2dfa74524} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP0R}

RTC backup register 0, Address offset\+: 0x50 \Hypertarget{struct_r_t_c___type_def_a5feba3d5adae3f234b3d172459163c5a}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP10R@{BKP10R}}
\index{BKP10R@{BKP10R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP10R}{BKP10R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a5feba3d5adae3f234b3d172459163c5a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP10R}

RTC backup register 10, Address offset\+: 0x78 \Hypertarget{struct_r_t_c___type_def_a8fef38e1e122778601e18f5b757c037a}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP11R@{BKP11R}}
\index{BKP11R@{BKP11R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP11R}{BKP11R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a8fef38e1e122778601e18f5b757c037a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP11R}

RTC backup register 11, Address offset\+: 0x7C \Hypertarget{struct_r_t_c___type_def_a6606b5d249f923aa15ab74b382cbaf7e}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP12R@{BKP12R}}
\index{BKP12R@{BKP12R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP12R}{BKP12R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a6606b5d249f923aa15ab74b382cbaf7e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP12R}

RTC backup register 12, Address offset\+: 0x80 \Hypertarget{struct_r_t_c___type_def_a138903d4681455a660dccbaf3409263d}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP13R@{BKP13R}}
\index{BKP13R@{BKP13R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP13R}{BKP13R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a138903d4681455a660dccbaf3409263d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP13R}

RTC backup register 13, Address offset\+: 0x84 \Hypertarget{struct_r_t_c___type_def_adaae50f5c3213014fb9818eaee389676}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP14R@{BKP14R}}
\index{BKP14R@{BKP14R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP14R}{BKP14R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_adaae50f5c3213014fb9818eaee389676} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP14R}

RTC backup register 14, Address offset\+: 0x88 \Hypertarget{struct_r_t_c___type_def_a797f43f9cc1858baebd1799be288dff6}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP15R@{BKP15R}}
\index{BKP15R@{BKP15R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP15R}{BKP15R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a797f43f9cc1858baebd1799be288dff6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP15R}

RTC backup register 15, Address offset\+: 0x8C \Hypertarget{struct_r_t_c___type_def_a181ad73082bde7d74010aac16bd373fc}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP16R@{BKP16R}}
\index{BKP16R@{BKP16R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP16R}{BKP16R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a181ad73082bde7d74010aac16bd373fc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP16R}

RTC backup register 16, Address offset\+: 0x90 \Hypertarget{struct_r_t_c___type_def_a90a305a8e00b357f28daef5041e5a8b1}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP17R@{BKP17R}}
\index{BKP17R@{BKP17R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP17R}{BKP17R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a90a305a8e00b357f28daef5041e5a8b1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP17R}

RTC backup register 17, Address offset\+: 0x94 \Hypertarget{struct_r_t_c___type_def_a171288f82cab2623832de779fb435d74}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP18R@{BKP18R}}
\index{BKP18R@{BKP18R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP18R}{BKP18R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a171288f82cab2623832de779fb435d74} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP18R}

RTC backup register 18, Address offset\+: 0x98 \Hypertarget{struct_r_t_c___type_def_a993f54e8feff9254f795dfd3e000fc55}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP19R@{BKP19R}}
\index{BKP19R@{BKP19R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP19R}{BKP19R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a993f54e8feff9254f795dfd3e000fc55} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP19R}

RTC backup register 19, Address offset\+: 0x9C \Hypertarget{struct_r_t_c___type_def_a5439bfca3708c6b8be6a74626f06111f}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP1R@{BKP1R}}
\index{BKP1R@{BKP1R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP1R}{BKP1R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a5439bfca3708c6b8be6a74626f06111f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP1R}

RTC backup register 1, Address offset\+: 0x54 \Hypertarget{struct_r_t_c___type_def_a3e391ffa70a17dc5f95a841b5ec7554c}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP20R@{BKP20R}}
\index{BKP20R@{BKP20R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP20R}{BKP20R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a3e391ffa70a17dc5f95a841b5ec7554c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP20R}

RTC backup register 20, Address offset\+: 0x\+A0 \Hypertarget{struct_r_t_c___type_def_a170847c24f166be0939a6eaeed7eeeee}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP21R@{BKP21R}}
\index{BKP21R@{BKP21R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP21R}{BKP21R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a170847c24f166be0939a6eaeed7eeeee} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP21R}

RTC backup register 21, Address offset\+: 0x\+A4 \Hypertarget{struct_r_t_c___type_def_a679ec46535cae5149dc4d84e7c5d985c}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP22R@{BKP22R}}
\index{BKP22R@{BKP22R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP22R}{BKP22R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a679ec46535cae5149dc4d84e7c5d985c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP22R}

RTC backup register 22, Address offset\+: 0x\+A8 \Hypertarget{struct_r_t_c___type_def_a7836b793c4ecc58a27733329f26550a7}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP23R@{BKP23R}}
\index{BKP23R@{BKP23R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP23R}{BKP23R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a7836b793c4ecc58a27733329f26550a7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP23R}

RTC backup register 23, Address offset\+: 0x\+AC \Hypertarget{struct_r_t_c___type_def_abfe68a89c3a7c2620bb0f286d3f58eea}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP24R@{BKP24R}}
\index{BKP24R@{BKP24R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP24R}{BKP24R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_abfe68a89c3a7c2620bb0f286d3f58eea} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP24R}

RTC backup register 24, Address offset\+: 0x\+B0 \Hypertarget{struct_r_t_c___type_def_a052e275100e4b202808fa4bbe9d5515d}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP25R@{BKP25R}}
\index{BKP25R@{BKP25R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP25R}{BKP25R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a052e275100e4b202808fa4bbe9d5515d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP25R}

RTC backup register 25, Address offset\+: 0x\+B4 \Hypertarget{struct_r_t_c___type_def_aaa12210df2df47a6276270a2b7b2d038}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP26R@{BKP26R}}
\index{BKP26R@{BKP26R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP26R}{BKP26R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_aaa12210df2df47a6276270a2b7b2d038} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP26R}

RTC backup register 26, Address offset\+: 0x\+B8 \Hypertarget{struct_r_t_c___type_def_a5879b0d3796b1c291f64dbaa57653624}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP27R@{BKP27R}}
\index{BKP27R@{BKP27R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP27R}{BKP27R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a5879b0d3796b1c291f64dbaa57653624} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP27R}

RTC backup register 27, Address offset\+: 0x\+BC \Hypertarget{struct_r_t_c___type_def_abd26829bfe028b5882d523e7035eb497}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP28R@{BKP28R}}
\index{BKP28R@{BKP28R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP28R}{BKP28R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_abd26829bfe028b5882d523e7035eb497} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP28R}

RTC backup register 28, Address offset\+: 0x\+C0 \Hypertarget{struct_r_t_c___type_def_aa240211cf23c5822f4ac9c690a7a248c}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP29R@{BKP29R}}
\index{BKP29R@{BKP29R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP29R}{BKP29R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_aa240211cf23c5822f4ac9c690a7a248c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP29R}

RTC backup register 29, Address offset\+: 0x\+C4 \Hypertarget{struct_r_t_c___type_def_aa845c401b24d2ef1049f489f26d35626}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP2R@{BKP2R}}
\index{BKP2R@{BKP2R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP2R}{BKP2R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_aa845c401b24d2ef1049f489f26d35626} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP2R}

RTC backup register 2, Address offset\+: 0x58 \Hypertarget{struct_r_t_c___type_def_a32b51e2f18c68ea5af816d1f231b7ec6}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP30R@{BKP30R}}
\index{BKP30R@{BKP30R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP30R}{BKP30R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a32b51e2f18c68ea5af816d1f231b7ec6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP30R}

RTC backup register 30, Address offset\+: 0x\+C8 \Hypertarget{struct_r_t_c___type_def_a4bccd0b2feecc2e2159898857bab6d89}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP31R@{BKP31R}}
\index{BKP31R@{BKP31R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP31R}{BKP31R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a4bccd0b2feecc2e2159898857bab6d89} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP31R}

RTC backup register 31, Address offset\+: 0x\+CC \Hypertarget{struct_r_t_c___type_def_ac3802c3b17482a0667fb34ddd1863434}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP3R@{BKP3R}}
\index{BKP3R@{BKP3R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP3R}{BKP3R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ac3802c3b17482a0667fb34ddd1863434} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP3R}

RTC backup register 3, Address offset\+: 0x5C \Hypertarget{struct_r_t_c___type_def_a6131b2f2896c122cf223206e4cfd2bd0}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP4R@{BKP4R}}
\index{BKP4R@{BKP4R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP4R}{BKP4R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a6131b2f2896c122cf223206e4cfd2bd0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP4R}

RTC backup register 4, Address offset\+: 0x60 \Hypertarget{struct_r_t_c___type_def_a0f3a33de81247ec5729e400a1261f917}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP5R@{BKP5R}}
\index{BKP5R@{BKP5R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP5R}{BKP5R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a0f3a33de81247ec5729e400a1261f917} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP5R}

RTC backup register 5, Address offset\+: 0x64 \Hypertarget{struct_r_t_c___type_def_a766e2071c5826e3a299ae1cd5bbf06f7}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP6R@{BKP6R}}
\index{BKP6R@{BKP6R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP6R}{BKP6R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a766e2071c5826e3a299ae1cd5bbf06f7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP6R}

RTC backup register 6, Address offset\+: 0x68 \Hypertarget{struct_r_t_c___type_def_a9934af6ae6b3f5660204d48ceb2f3192}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP7R@{BKP7R}}
\index{BKP7R@{BKP7R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP7R}{BKP7R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a9934af6ae6b3f5660204d48ceb2f3192} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP7R}

RTC backup register 7, Address offset\+: 0x6C \Hypertarget{struct_r_t_c___type_def_a0e7fca11f1c953270ee0ee6028860add}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP8R@{BKP8R}}
\index{BKP8R@{BKP8R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP8R}{BKP8R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a0e7fca11f1c953270ee0ee6028860add} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP8R}

RTC backup register 8, Address offset\+: 0x70 \Hypertarget{struct_r_t_c___type_def_abadf1ac26350bf00575428be6a05708b}\index{RTC\_TypeDef@{RTC\_TypeDef}!BKP9R@{BKP9R}}
\index{BKP9R@{BKP9R}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BKP9R}{BKP9R}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_abadf1ac26350bf00575428be6a05708b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+BKP9R}

RTC backup register 9, Address offset\+: 0x74 \Hypertarget{struct_r_t_c___type_def_aea66ea813830c2f3ff207464794397a4}\index{RTC\_TypeDef@{RTC\_TypeDef}!CALR@{CALR}}
\index{CALR@{CALR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CALR}{CALR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_aea66ea813830c2f3ff207464794397a4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+CALR}

RTC calibration register, Address offset\+: 0x3C \Hypertarget{struct_r_t_c___type_def_a731d9209ce40dce6ea61fcc6f818c892}\index{RTC\_TypeDef@{RTC\_TypeDef}!CR@{CR}}
\index{CR@{CR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a731d9209ce40dce6ea61fcc6f818c892} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+CR}

RTC control register, Address offset\+: 0x08 \Hypertarget{struct_r_t_c___type_def_a8750eae683cb3d382476dc7cdcd92b96}\index{RTC\_TypeDef@{RTC\_TypeDef}!DR@{DR}}
\index{DR@{DR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a8750eae683cb3d382476dc7cdcd92b96} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+DR}

RTC date register, Address offset\+: 0x04 \Hypertarget{struct_r_t_c___type_def_a5a7b104d80b48b5708b50cdc487d6a78}\index{RTC\_TypeDef@{RTC\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a5a7b104d80b48b5708b50cdc487d6a78} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+ISR}

RTC initialization and status register, Address offset\+: 0x0C \Hypertarget{struct_r_t_c___type_def_ac4ec213226146fa48aa9b29e0e80b3ad}\index{RTC\_TypeDef@{RTC\_TypeDef}!OR@{OR}}
\index{OR@{OR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OR}{OR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ac4ec213226146fa48aa9b29e0e80b3ad} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+OR}

RTC option register, Address offset\+: 0x4C \Hypertarget{struct_r_t_c___type_def_a5f43a11e0873212f598e41db5f2dcf6a}\index{RTC\_TypeDef@{RTC\_TypeDef}!PRER@{PRER}}
\index{PRER@{PRER}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PRER}{PRER}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a5f43a11e0873212f598e41db5f2dcf6a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+PRER}

RTC prescaler register, Address offset\+: 0x10 \Hypertarget{struct_r_t_c___type_def_a37afe665222962031d111527b7fd406b}\index{RTC\_TypeDef@{RTC\_TypeDef}!RESERVED@{RESERVED}}
\index{RESERVED@{RESERVED}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED}{RESERVED}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a37afe665222962031d111527b7fd406b} 
uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+RESERVED}

Reserved, Address offset\+: 0x18 \Hypertarget{struct_r_t_c___type_def_a6082856c9191f5003b6163c0d3afcaff}\index{RTC\_TypeDef@{RTC\_TypeDef}!SHIFTR@{SHIFTR}}
\index{SHIFTR@{SHIFTR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SHIFTR}{SHIFTR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a6082856c9191f5003b6163c0d3afcaff} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+SHIFTR}

RTC shift control register, Address offset\+: 0x2C \Hypertarget{struct_r_t_c___type_def_aefbd38be87117d1fced289bf9c534414}\index{RTC\_TypeDef@{RTC\_TypeDef}!SSR@{SSR}}
\index{SSR@{SSR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SSR}{SSR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_aefbd38be87117d1fced289bf9c534414} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+SSR}

RTC sub second register, Address offset\+: 0x28 \Hypertarget{struct_r_t_c___type_def_a498ecce9715c916dd09134fddd0072c0}\index{RTC\_TypeDef@{RTC\_TypeDef}!TAFCR@{TAFCR}}
\index{TAFCR@{TAFCR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TAFCR}{TAFCR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a498ecce9715c916dd09134fddd0072c0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+TAFCR}

RTC tamper and alternate function configuration register, Address offset\+: 0x40 \Hypertarget{struct_r_t_c___type_def_a2e8783857f8644a4eb80ebc51e1cba42}\index{RTC\_TypeDef@{RTC\_TypeDef}!TR@{TR}}
\index{TR@{TR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TR}{TR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a2e8783857f8644a4eb80ebc51e1cba42} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+TR}

RTC time register, Address offset\+: 0x00 \Hypertarget{struct_r_t_c___type_def_aa4633dbcdb5dd41a714020903fd67c82}\index{RTC\_TypeDef@{RTC\_TypeDef}!TSDR@{TSDR}}
\index{TSDR@{TSDR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TSDR}{TSDR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_aa4633dbcdb5dd41a714020903fd67c82} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+TSDR}

RTC time stamp date register, Address offset\+: 0x34 \Hypertarget{struct_r_t_c___type_def_a1e8b4b987496ee1c0c6f16b0a94ea1a1}\index{RTC\_TypeDef@{RTC\_TypeDef}!TSSSR@{TSSSR}}
\index{TSSSR@{TSSSR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TSSSR}{TSSSR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a1e8b4b987496ee1c0c6f16b0a94ea1a1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+TSSSR}

RTC time-\/stamp sub second register, Address offset\+: 0x38 \Hypertarget{struct_r_t_c___type_def_a1ddbb2a5eaa54ff43835026dec99ae1c}\index{RTC\_TypeDef@{RTC\_TypeDef}!TSTR@{TSTR}}
\index{TSTR@{TSTR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TSTR}{TSTR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_a1ddbb2a5eaa54ff43835026dec99ae1c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+TSTR}

RTC time stamp time register, Address offset\+: 0x30 \Hypertarget{struct_r_t_c___type_def_ad54765af56784498a3ae08686b79a1ff}\index{RTC\_TypeDef@{RTC\_TypeDef}!WPR@{WPR}}
\index{WPR@{WPR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPR}{WPR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ad54765af56784498a3ae08686b79a1ff} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+WPR}

RTC write protection register, Address offset\+: 0x24 \Hypertarget{struct_r_t_c___type_def_ad93017bb0a778a2aad9cd71211fc770a}\index{RTC\_TypeDef@{RTC\_TypeDef}!WUTR@{WUTR}}
\index{WUTR@{WUTR}!RTC\_TypeDef@{RTC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WUTR}{WUTR}}
{\footnotesize\ttfamily \label{struct_r_t_c___type_def_ad93017bb0a778a2aad9cd71211fc770a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RTC\+\_\+\+Type\+Def\+::\+WUTR}

RTC wakeup timer register, Address offset\+: 0x14 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
